(a) Field of the Invention
The present invention relates to a level shifter and a flat panel display including the level shifter. More specifically, the present invention relates to a level shifter for decreasing a low-level voltage in a system including PMOS transistors, or a level shifter for increasing a high-level voltage in a system including NMOS transistors.
(b) Description of the Related Art
A level shifter represents a circuit provided between two digital systems, for modifying values of signal voltages when coupling the two digital systems having different signal voltages. The level shifter is used for converting the signal voltage values in a low voltage range into those in a high voltage range.
FIG. 12 shows a circuit diagram of a level shifter according to a prior art.
As shown in FIG. 12, the conventional level shifter includes two PMOS transistors P1 and P2. In this instance, transistor P1 is coupled between high-level power VDD and an output end, and transistor P2 is diode-connected between the output end and low-level power LVSS.
In this conventional level shifter, when low level voltage VSS is applied to gate of transistor P1, high-level output voltage Vout is determined according to the on resistance ratio of transistors P1 and P2. When high-level voltage VDD is applied to gate of transistor P1, low-level output voltage Vout reaches a voltage (LVSS+|Vp|) higher than LVSS by the values of threshold voltage Vp of transistor P2.
In this instance, when decreasing LVSS so as to obtain a desired low-level output voltage, a high-level output voltage is decreased. When the high level output voltage is decreased as described above, a circuit that receives an output from a level shifter may detect the high-level output voltage as a low-level voltage. That is, when attempting to detect a high-level output voltage of the conventional level shifter as a high-level input voltage of another circuit, the low-level output voltage is not decreased to a desired level.